1. Field of the Invention
The present invention relates to an apparatus and method for connecting a processor to a bus.
2. Description of the Related Art
FIG. 1 is a block diagram of the structure of a related art dual bus path system. The related art dual bus path system comprises a first memory 11, an input apparatus 12, a processor 13, a bus controller 14, a second memory 15, and an output apparatus 16.
The first memory 11 is a space which the processor 13 uses for operations and the second memory 15 is a space in which display data are stored. The first memory 11 and the second memory 12 are connected to different buses. If the amount of display data is great and there is only one bus, the bus is easily filled to the limit of the transmission capacity. Accordingly, there is an additional bus which is used exclusively for transferring display data.
At present, due to the growing size of display screens and improvement in picture quality, the amount of data needed in a display apparatus increases and even the related art exclusive bus used for display is easily filled to the limit of the transmission capacity. The speed of the bus may be raised to solve the problem. However, there is a limit in raising the speed due to the relations with the processor clock, and raising the speed increases power consumption. In addition, other peripherals are required to be designed to operate at the raised speed.